In general, the manufacturing process of a semiconductor wafer is constituted by process flow in which a wafer obtained by slicing out from a pulled out silicon single crystal ingot is chamfered, mechanically polished (lapped), etched, mirror-polished (polished), and cleaned so as to be produced as a wafer having a highly accurate flatness.
The silicon wafer gone through machining process such as block cutting off, outer diameter grinding, slicing, lapping and the like has damaged layers, that is, degraded superficial layers in the surface. The degraded superficial layers induce a crystal defect such as a slip dislocation and the like in a device manufacturing process, and reduce mechanical strength of the wafer, and exert adverse effect on electrical characteristics, and therefore, must be completely removed.
To remove these degraded superficial layers, an etching processing is performed. The etching processing includes an acid etching using an acid etching solution, and an alkali etching using an alkali etching solution.
However, when the acid etching is performed, the flatness obtained by lapping is harmed, and a warp in mm order and unevenness called as peel are generated in the etching surface. Further, there has been a problem in that when the alkali etching is performed, a pit (hereinafter referred to as a facet) having a local depth of several μm and a size of approx several tens of μm is generated.
As the method of solving the above described problem, as shown in FIG. 7, in the processing method of the semiconductor wafer comprising a process of at least chamfering 2, lapping 3, etching 4 and 5, mirror-polishing 6, and cleaning the semiconductor wafer obtained by slicing 1 the single silicon crystal ingot, there is proposed a processing method of the wafer and the wafer processed by this method in which the etching process is performed by the alkali etching 4, and after that, by the acid etching 5, and at this time, an etching removal depth of the alkali etching is made larger than the etching removal depth of the acid etching 5 (for example, see Patent Document 1).
By the method shown in the Patent Document 1, the flatness after the lapping can be maintained, and the warp of the wafer surface after the etching can be reduced, and generation of the locally deep pit and deterioration of the surface roughness can be controlled. At the same time, it is possible to prepare a chemical etching wafer having an etching surface hard to develop contamination such as particles, stain, and the like. Such a wafer can reduce a removal depth in mirror-polishing, and improve the flatness.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 11-233485